Journal of Harmonized Research in Engineering

INSTRUCTION SET

Abstract

Author(s): Shweta Garg, Shrishti Vashist, Shruti Aggarwal

The ideal memory system alleged by most programmers is one which has high capacity, yet allows any word to be accessed immediately. To make the hardware estimated this performance, an increasingly complex memory hierarchy, using caches and techniques like automatic prefetch, has evolved. However, as the gap between processor and memory speeds continues to widen, these programmer-visible mechanisms are becoming inadequate.